Fat-Tree Routing for Transit

Title: en_US Fat-Tree Routing for Transit
Creator: en_US DeHon, Andre
Date: 2004-10-20T20:22:45Z
Date Available: 2004-10-20T20:22:45Z
Date Issued: en_US 1990-02-01
Identifier: en_US AITR-1224
uri: http://hdl.handle.net/1721.1/7026
Abstract: en_US The Transit network provides high-speed, low-latency, fault-tolerant interconnect for high-performance, multiprocessor computers. The basic connection scheme for Transit uses bidelta style, multistage networks to support up to 256 processors. Scaling to larger machines by simply extending the bidelta network topology will result in a uniform degradation of network latency between all processors. By employing a fat-tree network structure in larger systems, the network provides locality and universality properties which can help minimize the impact of scaling on network latency. This report details the topology and construction issues associated with integrating Transit routing technology into fat-tree interconnect topologies.
Extent: 4074548 bytes; 3944868 bytes
Format: application/postscript; application/pdf
Language: en_US
Relation: en_US AITR-1224