A Parallel Crossbar Routing Chip for a Shared Memory Multiprocessor

Item

Title: en_US A Parallel Crossbar Routing Chip for a Shared Memory Multiprocessor
Creator: en_US Minsky, Henry
Date: 2004-10-20T19:57:43Z
Date Available: 2004-10-20T19:57:43Z
Date Issued: en_US 1991-03-01
Identifier: en_US AITR-1284
uri: http://hdl.handle.net/1721.1/6810
Abstract: en_US This thesis describes the design and implementation of an integrated circuit and associated packaging to be used as the building block for the data routing network of a large scale shared memory multiprocessor system. A general purpose multiprocessor depends on high-bandwidth, low-latency communications between computing elements. This thesis describes the design and construction of RN1, a novel self-routing, enhanced crossbar switch as a CMOS VLSI chip. This chip provides the basic building block for a scalable pipelined routing network with byte-wide data channels. A series of RN1 chips can be cascaded with no additional internal network components to form a multistage fault-tolerant routing switch. The chip is designed to operate at clock frequencies up to 100Mhz using Hewlett-Packard's HP34 $1.2\\mu$ process. This aggressive performance goal demands that special attention be paid to optimization of the logic architecture and circuit design.
Extent: en_US 114 p.; 11927286 bytes; 4341163 bytes
Format: application/postscript; application/pdf
Language: en_US
Relation: en_US AITR-1284
Subject: en_US parallel processing; en_US multistage routing network; en_US computersarchitecture

Item sets: AI Technical Reports (1964 - 2004)