Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic

Item

Title: en_US Asymptotically Zero Energy Computing Using Split-Level Charge Recovery Logic
Creator: en_US Younis, Saed G.
Date: 2004-10-20T20:24:14Z
Date Available: 2004-10-20T20:24:14Z
Date Issued: en_US 1994-06-01
Identifier: en_US AITR-1500
uri: http://hdl.handle.net/1721.1/7058
Abstract: en_US The dynamic power requirement of CMOS circuits is rapidly becoming a major concern in the design of personal information systems and large computers. In this work we present a number of new CMOS logic families, Charge Recovery Logic (CRL) as well as the much improved Split-Level Charge Recovery Logic (SCRL), within which the transfer of charge between the nodes occurs quasistatically. Operating quasistatically, these logic families have an energy dissipation that drops linearly with operating frequency, i.e., their power consumption drops quadratically with operating frequency as opposed to the linear drop of conventional CMOS. The circuit techniques in these new families rely on constructing an explicitly reversible pipelined logic gate, where the information necessary to recover the energy used to compute a value is provided by computing its logical inverse. Information necessary to uncompute the inverse is available from the subsequent inverse logic stage. We demonstrate the low energy operation of SCRL by presenting the results from the testing of the first fully quasistatic 8 x 8 multiplier chip (SCRL-1) employing SCRL circuit techniques.
Extent: 3520683 bytes; 3812251 bytes
Format: application/postscript; application/pdf
Language: en_US
Relation: en_US AITR-1500

Item sets: AI Technical Reports (1964 - 2004)