Test Generation Guided Design for Testability

Title: en_US Test Generation Guided Design for Testability
Creator: en_US Wu, Peng
Date: 2004-10-20T20:00:56Z
Date Available: 2004-10-20T20:00:56Z
Date Issued: en_US 1988-07-01
Identifier: en_US AITR-1051
uri: http://hdl.handle.net/1721.1/6837
Abstract: en_US This thesis presents a new approach to building a design for testability (DFT) system. The system takes a digital circuit description, finds out the problems in testing it, and suggests circuit modifications to correct those problems. The key contributions of the thesis research are (1) setting design for testability in the context of test generation (TG), (2) using failures during FG to focus on testability problems, and (3) relating circuit modifications directly to the failures. A natural functionality set is used to represent the maximum functionalities that a component can have. The current implementation has only primitive domain knowledge and needs other work as well. However, armed with the knowledge of TG, it has already demonstrated its ability and produced some interesting results on a simple microprocessor.
Extent: en_US 129 p.; 13659756 bytes; 5291048 bytes
Format: application/postscript; application/pdf
Language: en_US
Relation: en_US AITR-1051
Subject: en_US artificial intelligence; en_US knowledge representation; en_US testsgeneration; en_US knowledge-based systems; en_US VLSI design for testability