A Parallel Crossbar Routing Chip for a Shared Memory Multiprocessor
Item
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Title
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en_US
A Parallel Crossbar Routing Chip for a Shared Memory Multiprocessor
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Creator
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en_US
Minsky, Henry
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Date
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2004-10-20T19:57:43Z
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Date Available
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2004-10-20T19:57:43Z
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Date Issued
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en_US
1991-03-01
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Identifier
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en_US
AITR-1284
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Abstract
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en_US
This thesis describes the design and implementation of an integrated circuit and associated packaging to be used as the building block for the data routing network of a large scale shared memory multiprocessor system. A general purpose multiprocessor depends on high-bandwidth, low-latency communications between computing elements. This thesis describes the design and construction of RN1, a novel self-routing, enhanced crossbar switch as a CMOS VLSI chip. This chip provides the basic building block for a scalable pipelined routing network with byte-wide data channels. A series of RN1 chips can be cascaded with no additional internal network components to form a multistage fault-tolerant routing switch. The chip is designed to operate at clock frequencies up to 100Mhz using Hewlett-Packard's HP34 $1.2\\mu$ process. This aggressive performance goal demands that special attention be paid to optimization of the logic architecture and circuit design.
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Extent
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en_US
114 p.
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11927286 bytes
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4341163 bytes
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Format
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application/postscript
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application/pdf
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Language
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en_US
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Relation
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en_US
AITR-1284
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Subject
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en_US
parallel processing
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en_US
multistage routing network
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en_US
computersarchitecture