A Coupled Multi-ALU Processing Node for a Highly Parallel Computer

Title: en_US A Coupled Multi-ALU Processing Node for a Highly Parallel Computer
Creator: en_US Keckler, Stephen W.
Date: 2004-10-20T19:57:35Z
Date Available: 2004-10-20T19:57:35Z
Date Issued: en_US 1992-09-01
Identifier: en_US AITR-1355
uri: http://hdl.handle.net/1721.1/6807
Abstract: en_US This report describes Processor Coupling, a mechanism for controlling multiple ALUs on a single integrated circuit to exploit both instruction-level and inter-thread parallelism. A compiler statically schedules individual threads to discover available intra-thread instruction-level parallelism. The runtime scheduling mechanism interleaves threads, exploiting inter-thread parallelism to maintain high ALU utilization. ALUs are assigned to threads on a cycle byscycle basis, and several threads can be active concurrently. Simulation results show that Processor Coupling performs well both on single threaded and multi-threaded applications. The experiments address the effects of memory latencies, function unit latencies, and communication bandwidth between function units.
Extent: en_US 165 p.; 19986107 bytes; 16194697 bytes
Format: application/postscript; application/pdf
Language: en_US
Relation: en_US AITR-1355
Subject: en_US runtime scheduling; en_US compile time scheduling; en_US parallelscomputers; en_US multithreading