Design and Evaluation of the Hamal Parallel Computer
Item
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Title
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en_US
Design and Evaluation of the Hamal Parallel Computer
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Creator
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Grossman, J.P.
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Date
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2004-10-20T20:00:24Z
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Date Available
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2004-10-20T20:00:24Z
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Date Issued
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2002-12-05
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Identifier
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AITR-2002-011
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Abstract
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Parallel shared-memory machines with hundreds or thousands of processor-memory nodes have been built; in the future we will see machines with millions or even billions of nodes. Associated with such large systems is a new set of design challenges. Many problems must be addressed by an architecture in order for it to be successful; of these, we focus on three in particular. First, a scalable memory system is required. Second, the network messaging protocol must be fault-tolerant. Third, the overheads of thread creation, thread management and synchronization must be extremely low. This thesis presents the complete system design for Hamal, a shared-memory architecture which addresses these concerns and is directly scalable to one million nodes. Virtual memory and distributed objects are implemented in a manner that requires neither inter-node synchronization nor the storage of globally coherent translations at each node. We develop a lightweight fault-tolerant messaging protocol that guarantees message delivery and idempotence across a discarding network. A number of hardware mechanisms provide efficient support for massive multithreading and fine-grained synchronization. Experiments are conducted in simulation, using a trace-driven network simulator to investigate the messaging protocol and a cycle-accurate simulator to evaluate the Hamal architecture. We determine implementation parameters for the messaging protocol which optimize performance. A discarding network is easier to design and can be clocked at a higher rate, and we find that with this protocol its performance can approach that of a non-discarding network. Our simulations of Hamal demonstrate the effectiveness of its thread management and synchronization primitives. In particular, we find register-based synchronization to be an extremely efficient mechanism which can be used to implement a software barrier with a latency of only 523 cycles on a 512 node machine.
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Extent
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186 p.
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14854547 bytes
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6844439 bytes
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Format
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application/postscript
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application/pdf
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Language
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en_US
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Relation
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AITR-2002-011
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Subject
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AI
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parallel
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network
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simulation
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hashing
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multithreading
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synchronization